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Automatically generated LDF file does not include SDRAM sections (SHARC)

Question asked by Phonon on Nov 26, 2012
Latest reply on Nov 27, 2012 by Phonon

I'm porting an existing VDSP++ 5.0 project to CCES 1.0.1, and I noticed that the automatically generated linker file, apart from many other differences, does not generate SDRAM mapping. Here's an excerpt from a LDF file generated with Expert Linker (VDSP++ 5.0) for ADSP-21489

 

...

  // ------------------------- BLOCK 3 -----------------------------------------

  // 0x000E 0000 to 0x000E 5554  Normal word (48) Space (1 Mbit RAM)

  // 0x000E 0000 to 0x000E 7FFF  Normal word (32) Space (1 Mbit RAM)

  // 0x001C 0000 to 0x001C FFFF  Short word (16)  Space (1 Mbit RAM)

  seg_heap { TYPE(DM RAM) START(0x000e0000) END(0x000e7fff) WIDTH(32) }

 

  // ------------------------- SDRAM -------------------------------------------

  // 0x00200000 to 0x009FFFFF  Normal word (32) Space (32MB RAM) as found on the

  // ADSP-21489 Ez-Board.

  //

  // Notes:

  // 1) For Code accesses, which are only supported in Bank 0 of External

  // port, address range is:

  //   - For VISA code (i.e 16bit accesses)     : 0x600000 - 0xFFFFFF

  //   - For NonVISA code (i.e 48 bit accesses) : 0x200000 - 0x5FFFFF

  //

  // 2) The linker does not understand address translation so does not detect

  // overlaps correctly which means that errors can be issued for non-

  // overlapping sections and also that no errors are issued for overlapping

  // sections. (TAR-43296)

 

  seg_ext_swco { TYPE(SW RAM) START(0x00600000) END(0x0065FFFF) WIDTH(16) }

  seg_ext_nwco { TYPE(PM RAM) START(0x00220000) END(0x0043FFFF) WIDTH(16) }

  seg_ext_dmda { TYPE(DM RAM) START(0x00660000) END(0x009FFFFF) WIDTH(16) }

  seg_ext_pmda { TYPE(DM RAM) START(0x00A00000) END(0x00AFFFFF) WIDTH(16) }

 

  seg_flash { TYPE(DM RAM) START(0x04000000) END(0x043FFFFF) WIDTH(8) }

  seg_sram { TYPE(DM RAM) START(0x0C000000) END(0x0C07FFFF) WIDTH(16) }

} /* MEMORY */

 

Here's the analogous linker file generated by CCES 1.0.1:

 

...

/*

   ** -------------------------- BLOCK 3 ---------------------------------------

   ** 0x000E 0000 to 0x000E 5554  Normal word (48) Space (1 Mbit RAM)

   ** 0x000E 0000 to 0x000E 7FFF  Normal word (32) Space (1 Mbit RAM)

   ** 0x001C 0000 to 0x001C FFFF  Short word (16)  Space (1 Mbit RAM)

   */

   mem_block3_dm32         { TYPE(DM RAM) START(0x000E0000) END(0x000E7FFF) WIDTH(32) }

 


   mem_sram                { TYPE(DM RAM ASYNCHRONOUS) START(0x0C000000) END(0x0C07FFFF) WIDTH(16) }

   mem_flash               { TYPE(DM RAM ASYNCHRONOUS) START(0x04000000) END(0x043FFFFF) WIDTH(8) }

  

   /*$VDSG<insert-new-memory-segments>                          */

   /* Text inserted between these $VDSG comments will be preserved */

   /*$VDSG<insert-new-memory-segments>                          */

  

} /* MEMORY */

 

Is there a reason this mapping isn't generated automatically? Is there a way to make CCES do that for me?

 

Cheers,

Andrei

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