Looking for a clock tree solution to fill the following requirements:
PCIe 3.0 (would like total jitter due to the generator / fanout to be less than 300fs if possible)
12 HCSL source terminated outputs. (all outputs will be 100MHz PCIe reference clock)
min 2 inputs (one from a fixed oscillator or crystal the other will be a HCSL source terminated input)
spread spectrum support.
prefer a 1 chip solution if possible.
This is part of a custom tester design to fan out either a on card generated reference clock or the clock from the host system.
What would folks suggest I look at to fill this need?