AnsweredAssumed Answered

SPI for AD1939 to BF532

Question asked by Yanko on Jul 31, 2009
Latest reply on Aug 8, 2009 by Yanko

Hi all, I am new here and I have a problem with initialize audio codec AD1939 to BF532 DSP. I wrote init code in C, but by simulation SPI registers and DMA aren't set and I don't understand this. In simulator windows shows SPI registers ( for example: SPI_CTL [n/a]) - What mean this? Initialize for SPORT0 work good. Can you help me for finding  my errors in code. I use for examples init code for codec AD1836 from BF533_EZ_KIT_LITE board. Thanks.

#include <ccblkfn.h>
#include <cdefBF532.h>
#include <defBF532.h>
#include <signal.h>
#include <stdio.h>

#define CODEC_1939_REGS_LENGTH   11

// SPI transfer mode
#define TIMOD_DMA_TX 0x0003

// SPORT0 word length
#define SLEN_32   0x001f

// DMA flow mode
#define FLOW_1   0x1000

int timer_count = 1;

// names for codec registers, used for iCodec 1939 TxRegs[]
#define PLL_Clock_Control0 0x0000
#define PLL_Clock_Control1 0x1000
#define DAC_CONTROL_0      0x2000
#define DAC_CONTROL_1      0x3000
#define DAC_CONTROL_2      0x4000
#define DAC_individual_mutes 0x5000
#define DAC_L1_VOLUME     0x6000
#define DAC_R1_VOLUME     0x7000
#define DAC_L2_VOLUME     0x8000
#define DAC_R2_VOLUME     0x9000
#define DAC_L3_VOLUME     0xA000
#define DAC_R3_VOLUME     0xB000
#define DAC_L4_VOLUME     0xC000
#define DAC_R4_VOLUME     0xD000
#define ADC_CONTROL_0     0xE000
#define ADC_CONTROL_1     0xF000
#define ADC_CONTROL_2     0x10000

volatile short sCodec1939TxRegs[CODEC_1939_REGS_LENGTH] =
{                          
         PLL_Clock_Control0 | 0x000,
         PLL_Clock_Control1 | 0x000,          
      DAC_CONTROL_0   | 0x000,
               DAC_CONTROL_1   | 0x000,
               DAC_CONTROL_2   | 0x000,
               DAC_individual_mutes | 0x000,
               DAC_L1_VOLUME  | 0x3ff,
               DAC_R1_VOLUME  | 0x3ff,
               DAC_L2_VOLUME  | 0x3ff,
               DAC_R2_VOLUME  | 0x3ff,
               DAC_L3_VOLUME  | 0x3ff,
               DAC_R3_VOLUME  | 0x3ff,
               DAC_L4_VOLUME  | 0x3ff,
               DAC_R4_VOLUME  | 0x3ff,
               ADC_CONTROL_0   | 0x000,
               ADC_CONTROL_1   | 0x180,
               ADC_CONTROL_2   | 0x000              
};


int tx_SPIbuffer[256];
int rx_SPIbuffer[256];

int Rx_buffer[256];
int Tx_buffer[256];

 

void init_SPORT0 (void)
{
//clear SPORT reg
*pSPORT0_TCR1 = 0;
*pSPORT0_TCR2 = 0;
*pSPORT0_RCR1 = 0;
*pSPORT0_RCR2 = 0;
// Sport0 receive configuration
// External CLK, External Frame sync, MSB first
// 32-bit data
*pSPORT0_RCR1 = RFSR;
*pSPORT0_RCR2 = SLEN_32;

*pSPORT0_TCR1 = TFSR;
*pSPORT0_TCR2 = SLEN_32;
  // Enable MCM 8 transmit & receive channels
   *pSPORT0_MTCS0 = 0x000000FF;
   *pSPORT0_MRCS0 = 0x000000FF;
  
   // Set MCM configuration register and enable MCM mode
   *pSPORT0_MCMC1 = 0x0000; //reset MCMC1
   *pSPORT0_MCMC2 = 0x101c; //set MCMC2
}

void init_DMA (void)
{
//configure DMA for SPORT0 Rx
*pDMA1_PERIPHERAL_MAP = 0x1000;
  // Configure DMA1
   // 32-bit transfers, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;

*pDMA1_START_ADDR = (void *)Rx_buffer [0] ;
   // DMA inner loop count
   *pDMA1_X_COUNT = 8;
   // Inner loop address increment
   *pDMA1_X_MODIFY = 4;
  
  //configure DMA for SPORT0 Tx
   *pDMA2_PERIPHERAL_MAP = 0x2000;
  
   // Configure DMA2
   // 32-bit transfers, Autobuffer mode
   *pDMA2_CONFIG =  WDSIZE_32| FLOW_1;
   // Start address of data buffer
   *pDMA2_START_ADDR = (void *)Tx_buffer [0];
   // DMA inner loop count
   *pDMA2_X_COUNT = 8;
   // Inner loop address increment
   *pDMA2_X_MODIFY   = 4;
}

void enable_DMA_sport0 (void)
{
// enable DMAs
   *pDMA2_CONFIG   = (*pDMA2_CONFIG | DMAEN);
   *pDMA1_CONFIG   = (*pDMA1_CONFIG | DMAEN);
  
   // enable Sport0 TX and RX
   *pSPORT0_TCR1  = (*pSPORT0_TCR1 | TSPEN);
   *pSPORT0_RCR1  = (*pSPORT0_RCR1 | RSPEN);
}
/*

*/
   
void init_SPI(void)
{
//Init SPI MASTER TX DMA
*pSPI_CTL = 0;
*pSPI_FLG = 0;

/* Set BAUD rate */
*pSPI_BAUD = 16;

/*use PF3 as spi device select */
*pSPI_FLG = FLS3; //ADC_LATCH

*pSPI_CTL =   SPE |       /* Enable SPI port */
    MSTR |       /* Master mode (internal SPICLK) */ 
    CPOL |       /* Active low SCK */
    SIZE |       /* 16-bit words */
               SZ |       /* Send zero or last word when SPI_TDBR is empty*/
            TIMOD_DMA_TX;      /* Start transfer with DMA read
        of SPI_RDBR, request further
        DMA reads as long as SPI DMA FIFO is not full*/


// Configure DMA5
   // 24-bit transfers
   *pDMA5_CONFIG = WDSIZE_32;
   // Start address of data buffer
   *pDMA5_START_ADDR = (void *)sCodec1939TxRegs;
   // DMA inner loop count
   *pDMA5_X_COUNT = CODEC_1939_REGS_LENGTH;
   // Inner loop address increment
   *pDMA5_X_MODIFY = 2;
               
// Map DMA5 to SPI
   *pDMA5_PERIPHERAL_MAP   = 0x5000;
  
/*Set up DMA5 to transmit*/                                      
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);      /* begin DMA */
}

void wait_SPI (void)
{
   unsigned int j;
   j = *pSPI_STAT;
  
   while (j & 0x0001 != 0x0001)
    j = *pSPI_STAT;   

 

void Init_Sport_Interrupts(void)
{
   // Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
   *pSIC_IAR0 = 0xffffffff;
   *pSIC_IAR1 = 0xffffff2f;
   *pSIC_IAR2 = 0xffffffff;

    // enable Sport0 RX interrupt
   *pSIC_IMASK = 0x00000200;
   ssync();
}

void main (void)
{
int b;
init_DMA ();

init_SPI ();
wait_SPI ();
enable_DMA_sport0 ();
init_SPORT0 ();
Init_Sport_Interrupts ();
while (1)
{
  b++;
}
}

 

Yanko Todorov.

Attachments

Outcomes