I'm working on an analog front end design that uses the AD9289 to convert pixel data from four high-speed image sensors. The design calls for the ADC and the image sensors to be clocked together at a nominal 10MHz.
I just noticed that the AD9289 datasheet specifies a maximum minimum clock rate of 12MHz, which has me concerned that the entire design is a wash. We are quite far along with the design (our engineer has already sent board for manufacture) so changes will be a major headache. We are working an an academic setting on grant money, so this isn't like a product where we can iterate as needed.
So I guess my question boils down to this: what is the lowest clock rate I can reasonably expect the AD9289 to function at?
If this simply won't work we could, in theory, redesign the front-end to double the clock to the ADC and then discard every other pixel, but that will create complexities elsewhere.
Thanks in advance!
I called and spoke with AD support. The gist of the issue is that capacitor droop will limit the lower sample rate, effectively lowering the resolution the slower you go. That said I was told that at 10MHz I was unlikely to see much, if any, effect, but that it would be part dependent. Since our application could suffice with a 4 bit ADC, we are set.