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ADF4351 load interface

Question asked by serg-ant on Nov 24, 2012
Latest reply on Nov 26, 2012 by serg-ant

Good afternoon!


I've just began using ADF4351 synthesizer and I've got some problems with PLL locking. It looks like PLL doesn't lock, but the frequency is correct.

So the lock detect signal still low. Have watched through the discussions about lock detect on this forum, but changing of lock detect precision to 10 ns led to nothing.


So I've got one question about load interface of  this chip. I'm using atxmega MCU on my board to program ADF4351. Since built-in SPI interface of ATxmega is 8-bit wide, so it is possible to load data only by 8 bits with pauses between them. In these pauses I don't deassert LE signal and there are no clock signals. Is it correct to load registers to ADF4351 in that way or clock and data signal should be without gaps?


I've attached the schematic time diagrams, sorry for bad drawing skills