In a dedicated prototype, I use an ADAU1445 to re-sample 16 input channels. I use 2x TDM8 as input and 2x TDM8 as output. BCLK and LRCLK are both slave(input/output), applying 48k on LRCLK0/LRCLK9 and 12.288MHz on BCLK0/BCLK9 (from 2 different clock domains).
For now, we focus on the first TDM data (8 channels):
My SDATA_OUT0 stays at logic '0' when system runs, but I see a full-scale signal in SDATA_IN0.
I see some a TDM signals on SDATA_OUT0 when I re-configure the output port 0 as master, but my hardware configuration cannot be used in that way (BCLK/LRCLK conflict).
I have also a ADAU1442 eval board, and tested the same software. It runs correctly in slave mode.
I use a micro-controller to boot the ADAU1445 in SPI mode, this seems to work correctly.
=> is the ADAU1445 different from the 1442? Any idea of the problem?
I've attached the project files and schematics.
We use SigmaStudio Version 3.7. Build 7, Rev 1097.
Thanks for your support,