AnsweredAssumed Answered

Trace lengths and widths for impedance matching

Question asked by HIDIR on Nov 20, 2012
Latest reply on Nov 21, 2012 by HIDIR

Hi,

I have AD6645 and AD9764 evaluation boards and Spartan 3AN FPGA development kit. I have a written VHDL code and want to verify its functioning using ADC and DAC data.

 

     The FPGA I use

xilinx-spartan-3an-starter-kit.jpg

has an I/O connector as in the website below

http://tr.farnell.com/hrs-hirose/fx2-100s-1-27dsl-71/recept-1-27mm-r-a-100way/dp/1874281

 

     The ADC evaluation board (http://www.ictradenet.com/models_pic/AD6645-105%5EPCB.jpg )

has a Header, 40-pin, male, right angle Samtec TSW-120-08-T-D-RA connector

http://tr.farnell.com/productimages/farnell/standard/2009460-40.jpg

 

     The DAC evaluation board

has an input connector : CONNECTOR HDR RTA 4 0 PIN P AMP 102159-9 PROTECTED, W/EJECTORS (DIGI-KEY) AHR40G-ND

 

I want to connect these 3 boards together. So i have ordered the mating connectors. Now i need to make a custom PCB that has the connectors, data and clock traces on it. What should the length and the width of the traces be that will not degrade the performance and cause problems with the digital clock and data signals ?

Do you have any suggestion about having a connection or trying another method ?

Also do you have any idea about clock synchronisation about the boards and the FPGA ?

Any help please .

Thank you very much

HIDIR

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