I expect one SPI master (aduc) providing clock (4-5 mbps) and several numbers (N) of slaves (also aduc) . Slaves are connected consecutive, so that MISO of one slave is linked to the MOSI of next slave. Each slave provides 2 bytes of specific information. The task is to download those 2 bytes from each slave to master with a maximum possible speed.
I can think of this system as about long shift register. At the moment of start of transferring data by master, there are 2 bytes of initial data in each slave, and then they shift down to master bit-by-bit.
How this could be done? What configuration should i use, what kind of interrupts?
Is SPIRX and SPITX physically different registers or it is one register?
Should I move (copy) input (received) data from input FIFO to the output FIFO or this can be done automatically?