To whom it may concern
I'm searching for a reference FPGA design of ad6645 and ad9764.
Is someone out there who has done such a design or can help me with this challange?
Yours with kind regards
Hi HIDIR -
Analog Devices does not have ready to use reference designs that interface these two products to FPGAs.
Hi Mr. Larry -
Thank you for your quick reply.
A pseudo code is also enough for me .
Looking at the timing diagram of AD6644
The data can be captured when ENCODE is LOW and DRY is HIGH. Actually after 3 clock cycles the sampled data (N) is outputted.
For the AD9764 again looking at the timing diagram
DAC input data can be captured when CLOCK is high and IOUTA is high.
All the data outputs from the ADC and the DAC are available at the same time because of parallel output interfaces.
Here is my VHDL code for only ADC
if (RST_IN='1') then
dmout<=(others => '0');
elsif rising_edge(dry) then
leds<=fmin(13 downto 0); # ADC output to leds
elsif rising_edge(CLKFX_OUT) then
dmout <= (not(fmin) + "00000000000001");# DAC input
I wonder if my pseudo code or idea of data capturing is right or not .
Do I need to make any timing consideration about the set up or holding times of the converters and the FPGA in my VHDL code ?
Unfortunately for the AD6645, we do not have a reference design for FPGA capture code. This device is ~14 years old, I would suggest that you could move to a newer product, such as the AD9650, which uses a Virtex 4 FPGA as its data capture reference design. Let me know if you decide to move in that direction and we can help.
I have already spent ~800$ for the evaluation boards and now I want to use them. Unfortunately it will be hard to buy them for my masters thesis.
As I have stated in the above response to Mr. Larry all i want is a pseudo code that is needed for data capture and the things i need to be careful about when capturing data form ADc and feeding to DAC using an FPGA. It seems it will take a long time for me to understand and test .. That is why i could not finish my masters on time .
Please if you have any piece of code or any ideas about both ADC and DAC data capture steps let me know .
Any help i will appreciate.
I sent you a personal email with a license agreement and FPGA reference design for the AD9258, a dual CMOS output ADC which is similar to the AD6645. Hopefully that will be useful as a starting point.
Hi Mr. David,
Thank you very much for your mail, i will take a look at it.
I have made a parametric search about the converters :
It is seen that both AD6644-45 and AD9258 have parallel oputput data formats and they have pipelined ADC architectures. I thought that the output bits should be sampled at the same time. However in the AD9258 FPGA reference design the code is based on an SPI interface. Should the data be captured serially (bit by bit; thus I need 14 clock cycles at least) or can I have the data (all the 14 bits) at one clock cycle ?
AD6644-45 does not have SPI control pins. Is it enough Tto sample data when ENCODE is LOW and DRY is HIGH as stated in my second reply ?
THe intention of the DRY signal is to to allow data capture during the rising edge of DRY , so it is edge, not level triggered. Also, the DRY is provided so that users do not have to use the sample clock (ENCODE) to also capture data. Trying to use the sample clock to also drive the data receiver can often corrupt the sample clock, leading to performance degradation of the ADC performance. The reference design I sent uses an edge triggered data capture.
Thank you Mr. David. THen I need to take samples at the rising edge of DRY signal.
In my evaluation board OPT_LAT is connected to BUFLAT by a resistor (DRY signal is not connected to the output connector).
However in the AD6645 evaluation board the DR_OUT is connected to BUF_LAT as shown below :
and the schematic :
This connection makes the clock signal of the flip flops be DR_OUT . Am I right ?
How should I use DRY, is it OK taking it out using a piece of cable ?
As you note, on our AD6645 eval board DRY(DR_OUT) is typically connected to BUFLAT through jumper E1. BUFLAT in-turn provides the CLOCK signals to the AD6645's output data latches U2/U7, as well as the Data Clock Output for our HSC-ADC-EVALB-DCZ data capture card via pin 37 of output connector J2.
DRY is essentially an inverted and delayed replica of the Encode Clock and shares the same fundamental output driver capabilities as the OVR and Data Output Bits (see d/s fig 35). These output driver levels and timings are characterized and spec'd using ~10pF loads as noted in d/s table 2.
So while accessing DRY directly from your brd design via cable/wire may work at the output rates supported by the AD6645, you will need to be sure that excessive loading of the DRY output is minimized, or kept similar to the other Data Output Bits. This will help insure the inherent timing relationship/skews between DRY and DATA are maintained as illustrated in d/s timing diagram Fig 2.
Hi Mr. Tony,
Thank you for your reply.
Is it OK if U2/U7 output data latches are sampled by DRY?
Yes, that's exactly how our AD6645 Eval Brd is typically configured as shown in the attached EVB schematic:
AD6645 DRY output > DR_OUT > BUFLAT(via E1 jumper) > U2/U7 CLOCK
The only difference it seems is that we also route the BUFLAT signal to U6 which drives the AD6645 DRY output off the EVB via pin 37 on connector J2. We use the signal from J2(pin 37) as the DATA CLOCK OUTPUT signal to latch/sample the ADC Data Bits from U2/U7 "into" our Digital Receiver FIFO Logic on our HSC-ADC-EVALB-DCZ capture card.
What signal/reference source does your design use to latch/sample the AD6645 Output Data "into" your FPGA receiver?
Thank you Mr. Larry Welchusa, Mr. Tony, Mr. David Buchanan and Mr. Andy for your valuable suggestions, comments and help.
Finally I am able to get data from AD6645 evaluation board and feed AD9764 evaluation board using Spartan 3 AN FPGA. Here are the pictures of the experimental system, the results in Chipscope and oscilloscope for 1 MHz input sine wave (DAC output, since the configuration consists of taking analog signal to AD6645 then to FPGA then to AD9764).
Oscilloscope view of DAC output:
In a few days instead of cables i will use circuit board to connect all the boards together.
I have another question.
AD6645 EVM is shipped with onboard 105 MHz clock oscillator which has the following features a load capacitance of 50 pF, +-100ppm, 10ms of max setup time. I need to sample the incoming ADC data with 16 MHz because of the FPGA code. However AD6645 has a minimum sampling rate of 30MHz. Instead of changing my FPGA code i think about three possible solutions.
The first of them is downsampling (decimating) the ADC data but this consumes FPGA design area and ADC output synchronization is hard.
In the second one i try to use two DCM's to create ADC sampling clock of a multiple of 16 MHz and a 16 MHz clock for AD9764 and signal processing in the FPGA code.
As a third method i want to put another clock oscillator on the AD6645 ADC EVM module instead of the shipped one (AC53R, 105 MHz) and dividing this clock by the required value to obtain 16 MHz clock which is synchronised with the ADC clock.
What is your suggestion about this subject? What are the specifications needed for the ADC clock oscillator? Will there be a change in the load capacitance, setup time specifications if I use for example a 64 MHz clock instead of the 105 MHz clock given? Is there any clock oscillator suggestions for the ADC sampling at 16x MHz? (one can be like the one in AD6644 evm datasheet : MXO45LV). Because when I used some oscillators I was not able to get data usign chipscope because it says the clock signal is too slow.
Thank you very much,
The AD6645 CLK input on the eval brd is AC-coupled so small variations in source xtal loading are acceptable. The most critical CLK source parameters with regards to maximizing 14-bit SNR performance are phase noise/jitter. Maintaining a low phase noise/jitter ADC CLK source becomes even more critical as the Ain frequency increases.
Luckily your lower 1MHz Ain target frequency will give you a little extra margin with respect to CLK jitter. Please refer to Fig 42 on AD6645 datasheet pg 19 for a chart detailing the relationship between ADC SNR vs CLK jitter for a given Ain frequency. Any crystal which meets the desired target jitter specs in fig 42 should result in acceptable AD6645 SNR performance. I'm also attaching AN-835 which provides details on various recommended ADC CLK sources and how we test/characterize high performance ADC's here at ADI.
In addition to the eval brds fixed on-board xtal CLK source, if you have access to a high quality sine-wave generator you can also use its filtered output as a CLK source to the AD6645 eval brd via Encode Connector J4 (shown in eval brd schematic earlier in this thread). You may be able to find a sig gen that includes provisions for outputting a time/phase synchronized lower frequency (divided) CLK output that could be used to CLK your 16MHz FPGA capture. As you noted, the AD6645 supports a minimum CLK sampling rate of 30MSPS.
Thanks Mr. Tony, i will try it .
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