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AD9789 VSB Modulator MER(SNR) issues

Question asked by Harry.Cho on Nov 15, 2012
Latest reply on Nov 18, 2012 by Harry.Cho

Dear All,

 

I have designed direct up conversion VSB modulator using AD9789+AD9516+AD914+FPGA and most of circuits are same with ADI evaluation board. My Fdac clock is 2.410Ghz and SRRC doing FPGA in my design. I have measured 38dB of  MER(SNR) in 57MHz and  24dB at 861MHz.  I have measured MER in  valid frequency range between 57MHz to 861MHz. I found that MER is slightly decreasing when I go higher frequency range. Is this normal situation? If not, please advice me how to increase MER in high frequency band.

 

My setting values of AD9789 are as following;

 

write_ad9789(0x30,0x80);

write_ad9789(0x31,0xf0);

write_ad9789(0x32,0x9e);

 

// harry test

write_ad9789(0x36,0x00);

write_ad9789(0x38,0x00);

 

// mu

write_ad9789(0x24,0x00);

write_ad9789(0x24,0x80);

 

write_ad9789(0x2f,0xff);

write_ad9789(0x33,0x42);

write_ad9789(0x39,0x4e);

write_ad9789(0x3a,0x6c);

 

write_ad9789(0x03,0x00);

write_ad9789(0x04,0xfe);

write_ad9789(0x03,0x0c);

write_ad9789(0x33,0x43);

 

//Set up digital datapath.

 

write_ad9789(0x06,0xd0);

 

// bast work around by harry

write_ad9789(0x08,0x48);

write_ad9789(0x09,0x15);

 

// nco 0 frequency tuning word register

//A9E7FF(100mhz for test purpose)

write_ad9789(0x0a,0xff);

write_ad9789(0x0b,0xe7);

write_ad9789(0x0c,0xa9);

 

// Rate converter q

//800000

write_ad9789(0x16,0x00);

write_ad9789(0x17,0x00);

write_ad9789(0x18,0x80);

// Rate converter p

//700000

write_ad9789(0x19,0x00);

write_ad9789(0x1a,0x00);

write_ad9789(0x1b,0x70);

 

// bpf center frequency

//A9E

write_ad9789(0x1c,0x9e);

write_ad9789(0x1d,0x0a);

 

// interface configuration register

write_ad9789(0x20,0x00);

write_ad9789(0x21,0x59);

 

// dco frequency

// internal clock phase adjust

write_ad9789(0x22,0x20);

write_ad9789(0x23,0x00);

 

// channel gain

// if 0 -> rf mute

write_ad9789(0x25,0x00);

 

// write spectral inversion

write_ad9789(0x29, 0);

 

// write full scale current -20ma full scale range

write_ad9789(0x3c,0x00);

write_ad9789(0x3d,0x02);

 

do

{

rdata = read_ad9789(0x04);

_delay_ms(1);

}

while (rdata != 0x08);

 

// update frequency register

write_ad9789(0x1e,0x80);

 

// update interface clock

write_ad9789(0x24,0x00);

write_ad9789(0x24,0x80);

 

// only channel 0 enable

write_ad9789(0x05,0x01);

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