I use LX9 Board driven AD7982. reference AD7980verilog.v. simulation AD7980verilog.v. access to the following figure:
Andrei reply such as:
The simulation is the difference: adc_clk_i (= adc_sclk_o) set different,I set 50MHZ,and he set 60MHz.Clock to be applied to ADC to read the conversions results,must be greater than 60MHz?