AnsweredAssumed Answered

AD7980 Pmod Xilinx FPGA Reference Design

Question asked by yuxiao on Nov 13, 2012
Latest reply on Nov 19, 2012 by awalshe

I use LX9 Board driven AD7982. reference AD7980verilog.v. simulation AD7980verilog.v. access to the following figure:

2011-11-10 13 05 59.jpg

Andrei reply such as:

sim.png

The simulation is the difference: adc_clk_i (= adc_sclk_o) set different,I set 50MHZ,and he set 60MHz.Clock to be applied to ADC to read the conversions results,must be greater than 60MHz?

Outcomes