In Rev.D is a note, that A[2:0] and Y[5:0] have all to be logic 1 to enable the SCP (3-wire SPI).
In Rev.E (11/2012) this note is missing.
I intend to use the chip in SCP-Mode for driving a GTP of a Xilinx Spartan 6.
How do i realize a clock < 160MHz before reconfiguration? If i have to set all pins to 1, the resulting clock is above 800MHz.
according to Rev.E, i would set Y="000111", but then is the SCP usable?