I want to build a direct conversion receiver that covers the frequency range of several 10 kHz to 3 MHz. The demodulator is a commutating mixer, which needs a (digital) 4-phase clock running up to 3 MHz.
The idea is to use the sine output of a DDS generator AD9833 or AD9834, feed it through a comparator and a counter which generates the 4-phase clock signal. The clock needs to run continuously, even when changing the frequency a small or large amount, this probably prevents using a PLL-based clock where the dividers need to be switched.
The problem that I see is that the comparator has to switch on the zero-crossings of the sine signal, however since it comes from a DAC with a 25 MHz or 75 MHz update rate, there will be significant peak-to-peak jitter: 40 ns or 13 ns.
If I pass the sine wave through a low-pass filter, say a mini-circuits SCLF-4.7, the 25 MHz or 75 MHz components should be attenuated by 50 dB, but what does this do on the jitter?
PS: Another question is: How does the jitter influence the characteristics of the receiver; but I do not expect this question to be answered in this forum. However, a pointer to some paper would be appreciated :-)