Hello, I hope someone help me.
According to EE-179, "It is important to make sure that the FPGA or ASIC which connects to Link Port 1, 2, or 3’s Block Completion pins doesn’t have any internal pull-down resistors active while /RST_IN is asserted (low). If the FPGA or ASIC has a pull-up this is ok".
Does it mean that if the pins connect to Link Port 1, 2, or 3’s Block Completion pins are pulled up or three-state, it is ok under. I don't need test mode.