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ADV7619 : TMDS PLL, CLK locked but DE signal , vSync filter not locked

Question asked by adithyam on Nov 7, 2012
Latest reply on Nov 7, 2012 by mattp

Hi,

 

I am using ADV7619 as HDMI sink with HDMI connected to port a. I am setting various modes enumerated by video driver. After setting each mode , I am reading the 0x98,0x6A register to check the DE regeneration status and Vsync status before getting the timing info. However For some of the modes the status bits mentioned are not locked (TMDS PLL and TMDS CLK are locked).  But for other I am getting correct values.

 

I repeated the same experiment with port B. For all the modes, the timings are coming fine with no failures. This happens consistently.

 

Am I missing something?

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