I want to control a digital interface (SPI signals, /RESET, /CLR etc.) with an FPGA. When the system powers up the interface pins will be floating until the FPGA can configure them.
Is that ok?
In general, all digital inputs should be driven to a high or low logic level as defined in the data sheet. For a case where the pins are not configured on power up it is recommended that pull-up or pull-down resistors (10K to 1M is usually OK) are used to pull the pins to defined states.
When configuring the pins it is also advisable to set the logic level to be the same as where the resistor is pulling the pin to.
For example, if a pin is using a pull-up resistor the pin should be configured so that it goes high when it is set as an output.
If the pin uses a pull-up resistor and is configured so that it goes low when it is enabled you will have the case where the voltage on the pin rises with Vdd when the pin is tri-state and then goes low when it is configured. This could appear to the interface as a transition on the pin which was not intended.
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