Hello Everyone,

I am using an 18.432MHz TCXO with +/-0.28ppm Frequency Stability vs Temperature. I am feeding this as REFCLK to the AD9913. With PLL Multiplication set to x13, i get a SYSCLK of 239.616MHz. I am generating an output of 32MHz Sinewave. What will be the Frequency Stability of the whole unit vs Temperature...? Will it remain +/-0.28ppm...? or Will it also increase....?

Advance Thanks and Regards,

Venugopal YS

Hi Venugopal,

Thank you for your patience.

All of our DDSs' internal PLL stays locked as long as it is within the stated operating condition. That is,

there should be no frequency drift vs. temperature variations. But, this assuming the REF CLK source driving the PLL does not drift vs. temperature. So, if you are using an 18.432MHz TCXO with +/-0.28ppm Frequency Stability vs Temperature,that should remain +/-0.28ppmas long as you are operating AD9913 and the TCXO according to its specifications. But, it's still recommended to use a 25MHz crystal as reference clock for AD9913.Unfortunately, if you really want the data for the DDS output frequency drift vs. temperature variations, there is no available data. Here's the explanation: If the reference clock source is stable and you thermally shock the PLL, you would get frequency variation at the output but that would depend on the loop bandwidth and other factors. For example, if you had a low loop bandwidth and there's a drastic temperature spike, the PLL would take longer to recover. A wider loop bandwidth would take less time to recover. If the temperature is not a drastic variation, and you have a sufficient loop bandwidth, then the PLL may have no measurable frequency drift. There are a lot of variables to consider that's why there's no performance characteristics for frequency drift vs. temperature with PLL enabled.

Hope this helps.

Best Regards,

Sitti