Good morning. I have a customer that is going to interface with the AD5254 via a Xilinx Spartan-6 FPGA and he has a couple of questions.
1) In Figure 29 of the data sheet, it indicates that the slave is generating the stop condition when all of the other figures indicate that the master issues the stop condition as is usually the case with I2C? Is the data sheet correct or is this a typo and the "P" box in Figure 29 should really be gray instead of white?
2) The customer wants to use the NOP command (Figure 31) to set the RDAC address from which he can the follow the NOP command with a current READ command (Figure 29). As I read the data sheet and Figure 31, you can only set the three address bits in the NOP command to read EEMEM locations 0 thru 7. However, the customer has downloaded a VHDL model for the AD5254 and his simulations are failing because the model is not behaving in this manner for the case where a NOP quick command is issued. The model seems to keep two separate address registers - one for the normal command case and one for the quick commands. So the address for the quick command was saved, but it was not transferred to the other address register that would be used on the next current read command. Is this the correct operation or a flaw in the model?
Richard A. Pensabene