We have previously designed with the ADV7181C when it was a new device.
At the time, the data suggested it could support the digitization of SXGA video (1280x1024 @ 60Hz, 108MHz pixel clock) over a restricted subset of its normal (-40 to +85C) operating temperature range - as I recall this restriction applied to the DDR data format, presumably because the pixel interface could not signal reliably at such high speeds over the full temperature range.
This mode appears to have been deleted from more recent data, yet the ADCs are still described as being capable of 110MHz digitization.
In a new application, we'd like to digitize a monochrome SXGA
(1280x1024) video source. I would therefore propose running the pixel interface in SDR (4:2:2) mode; the loss of chroma resolution is irrelevant (it's monochrome). The pixel clock will still be 108MHz. Is this feasible? If so could I power down all but one of the ADCs to save power?
If not, would it be feasible to reduce to horizontal resolution, e.g. to 1024? The pixel clock would then reduce to 86.4MHz.
It is important that we can operate over the full temperature range in this new requirement.
Any feedback will be greatly received.