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AD9914/15 PLL Feedback divider N - what's the relationship?

Question asked by ro@cxt.dk on Nov 1, 2012
Latest reply on Nov 1, 2012 by DSB

In the Rev A DS, Table 19 description of Feedback divider N states:

"Sets the feedback divider of the PLL. The divider range is 8× to 255×.

Bits[15:8] = 0000 = 8×, 0001 = 9× … 1111 = 255×"

When calling out 8 bits as in Bits[15:8] it would be logical to list 8, not 4 bits.  So it would read more like:

"Sets the feedback divider of the PLL. The divider range is 8× to 255×.
Bits[15:8] = 00000000 = 8×, 00000001 = 9× … 11111111 = 255×"

But that does not make sense either, as 11111111 would be 255+8 = 263... So how exactly is the relationship between the 8 bits of CRF3 and the divider N?

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