Please let me know if there is "power-up-sequence" of AD5684R.
"Absolute max rate"would be say no "power up/down sequence" ,I think.
but the timing characteristic say 1.8<= VLOGIC <= VDD on a margin.
it's just test condition, I think, but.
These kind of devices need to fix the logic first before VDD supply, I think.
but POR circuit was design on VDD side.
Please tell me how to think.