What is the minimum pulse width of the SYNCIO signal in order to reset the serial interface communication?
Does CS need to be asserted (low) for SYNCIO to have effect? (would be natural, but the information is missing from the DS).
If IO_UPDATE setup and hold times are not followed (i.e. if the signal is controlled by a simple I/O pin of a microcontroller), what would happen? Assuming a meta-stable flop inside the chip, but what would be the effect?
Assuming the exact timing of the register update is not important, is there a way to avoid an external flip-flop to synchronize the IO_UPDATE signal, when driving the signal from a simple microcontroller (on another clock)?