I am using AD9467 250MSPS ADC on my board (schematic attached) for sampling 2 input frequency ranges --- 180MHz +/- 40MHz as well as 70MHz +/- 2.5MHz. The ADCs are being operated at 250MSPS sampling rate. I had designed the circuit referring to http://www.analog.com/CN0227 guidelines with the filter cut-off frequency set to 400MHz. When I measured the SNR & SFDR values from the data captured from the ADC using VisualAnalog (plot attached), I am getting only around 48.5dBFS and SFDR of only 49.442dBc. My requirement is an SNR value greater than 70dBFS and SFDR greater than 80dBc. How can I improve these figures on my board?