We are using AD9889B to interface to HDMI TV.
I wanted to know how Register 0x17 bits [6:5] work when 0x41=0.
Do they provide the flexibility to invert the incoming HSYNC/VSYNC?
0x17[6:5] only effect the embedded syncs. There is no way to invert VS and HS pins as the signals come in.
The AD9x89B Programing Guide Rev A , page 73 , 0x17[6:5] lines define different 0x41 cases.
Basically you can pass through the sync or invert it.
I am trying to display 640x480p video.
CEA-861D defines the hsync/vsync poIarity to be negative for this resolution.
But the source of video only send out positive hsync/vsync to AD9889B.
Will configuring inversion of hsync/vsync help in this case?
Thanks. Thats helpful. I will switch to embedded syncs.
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