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spice error in Altium designer about AD8429

Question asked by Left on Oct 23, 2012
Latest reply on Oct 26, 2012 by krisf

AD8429.CKT

* AD8429 SPICE Macro-model

*

* Description: Amplifier

* Generic Desc: 36V Bipolar Low Noise InAmp G1-1000

* Developed by: ADN IAP ADI

* Revision History: 10/11/2012 - Updated to new header style

* 4.0 (10/2012)

* Copyright 2012 by Analog Devices.

*

* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model

* indicates your acceptance with the terms and provisions in the License Statement.

*

* BEGIN Notes:

*

* Not Modeled:

*   Temperature effects

*   PSRR

*   1/f Noise

*

* Parameters modeled include:

*   CMRR

*   Wideband noise

*   Bandwidth

*   Gain

*   Step response

*   Offset voltage

*   Bias current

*   Quiescent current

*   Output range vs. load

*

* END Notes

*

* Node assignments

*                 inverting input

*                 |   RG

*                 |   |    RG

*                 |   |    |  non_inverting input

*                 |   |    |    |    negative supply

*                 |   |    |    |    |    ref

*                 |   |    |    |    |    |   output

*                 |   |    |    |    |    |    |     positive supply

*                 |   |    |    |    |    |    |     |

.SUBCKT AD8429  IN-  RG-  RG+  IN+  -Vs   REF  VOUT  +Vs

R1 sub_out sub_neg 5E3

R2 sub_neg Inverting_Out 5E3

R3 sub_pos noninverting_out 5002.1

R4 REF sub_pos 5E3

R5 RG- N003 3e3

R6 RG+ N010 3000

D3 N003 P001 D

D4 P002 N003 D

V3 P002 VNEGx 0.94

V4 VPOSx P001 .71

D5 N010 P003 D

D6 P004 N010 D

V5 P004 VNEGx 0.94

V6 VPOSx P003 .71

D7 N005 P005 D

D8 P006 N005 D

V7 P006 VNEGx 2.5

V8 VPOSx P005 3.2

D9 N016 P007 D

D10 P008 N016 D

V9 P008 VNEGx 1.5

V10 VPOSx P007 3.2

D11 N009 P009 D

D12 P010 N009 D

V11 P010 N017 2.2

V12 N008 P009 1.55

D13 REF P011 D

D14 P012 REF D

V13 P012 VNEGx .3

V14 VPOSx P011 .3

D15 sub_pos P013 D

D16 P014 sub_pos D

V15 P014 VNEGx 0.9

V16 VPOSx P013 0.9

E4 Inverting_Out 0 N003 0 1

E5 noninverting_out 0 N010 0 1

V1 VBIAS +Vs 20

I1 VBIAS Pos_Fdbk 660E-6

I2 VBIAS Inv_Fdbk 660E-6

C1 N003 Inv_Fdbk 11e-12

C2 N010 Pos_Fdbk 11e-12

E8 N002 0 N005 0 1

E9 N013 0 N016 0 1

VOSI_Neg N004 IN- 50E-6

VOSI_Pos IN+ N014 49E-6

VOSO VOUT N009 575E-6

C3 RG- 0 12e-12

C4 RG+ 0 11.45e-12

I23 IN- 0 -30E-9

I24 IN+ 0 -25E-9

G1 0 IN+ N018 N019 .0025e-9

R13 IN+ N018 10e9

R14 N018 IN- 10e9

R15 +Vs N019 10e9

R16 N019 -Vs 10e9

G2 0 IN- N018 N019 .0025e-9

E10 VPOSx 0 +Vs 0 1

I3 +Vs -Vs 6.7e-3

G3 +Vs -Vs +Vs -Vs 2e-6

E11 VNEGx 0 -Vs 0 1

H1 VPOSx N008 POLY(1) VOSO 0 0 8000

H2 N017 VNEGx POLY(1) VOSO 0 0 8000

H3 N006 N004 V24 0.352

V24 N001 0 0

R19 N001 0 .0166

H4 VX sub_out V25 39.45

V25 N007 0 0

R20 N007 0 .0166

H5 N015 N014 V26 0.352

V26 N011 0 0

R21 N011 0 .0166

G4 0 N005 N006 N005 1

G5 0 N016 N015 N016 1

G6 0 N003 VBIAS Inv_Fdbk 1

G7 0 N010 VBIAS Pos_Fdbk 1

G8 0 sub_out sub_pos sub_neg 1

R10 N005 0 10e9

R7 N003 0 10E9

R11 N016 0 10E9

R8 N010 0 10E9

R9 sub_out 0 10E9

Q1 Pos_Fdbk N013 RG+ 0 NPN

Q2 Inv_Fdbk N002 RG- 0 NPN

G9 0 N012 VY N009 1

G10 0 N009 N012 0 8.32e-3

R12 N012 0 1e9

R17 N009 0 120.13

C5 N012 0 1.06e-8

C6 N009 0 180e-12

C8 VY 0 1e-9

G11 0 VY VALUE = { LIMIT( 1*V(VX,VY), .025, -.025) }

R22 VY 0 1e9

R18 VBIAS Inv_Fdbk 1e9

R23 Pos_Fdbk VBIAS 1e9

D1 sub_out P015 D

V2 VPOSx P015 1.55

D2 P016 sub_out D

V17 P016 VNEGx 2.2

I4 +Vs 0 -1.3e-3

.model D D

.model NPN NPN

.model PNP PNP

.ENDS AD8429

 

ERROR:

XSpiceError on line 115: g11\x* 0 vy\x* value = { limit( 1*v(vx\x*,vy\x*), .025, -.025) }

Outcomes