We are getting latch-up in the AD7376ARWZ10 digital pot which we run off +/-15V supplies.
There are short periods (200ms) where the VDD & VSS (+/-15V) supplies are not powered fully and yet signals are being input to the device : either 5 V logic signals, or the A,W,B inputs.
To reduce the problem Im trying to limit the current of the incoming signals. Is there a maximum current that the chip can handle without going into latch-up when the rails are not fully powered ? eg: 20mA.
Or is latch-up purely determined by the voltage at a point in time eg: even a very current limited signal greater than the rail will/may cause latch-up.?
Is there a typical limit ?
As I have to retro fit a fix, I am looking for simple fixes before we change the design to totally resolve the issue.
Thanks for any help.