I am using AD9517-4 to generate 160MHz differential clocks from 40MHz single ended reference using internal PLL and VCO. I have some queries regarding it.
- I am not using the LVPECL outputs and two pairs of differential LVDS outputs so what will be the proper termination required for these outputs.
- Should i use the loop filter as given by ADIsimCLK tool for AD9517 or can I change it and does the loop filter selection in any way affects the jitter performance in output clocks ?
Thanks and Regards,