We are using the AD9783 16-bit DAC on my board interfaced to a Xilinx Virtex6 FPGA. When we try to access the SPI interface of the DAC, for all register reads we are getting 0xFF as return value. We are using the 4-wire SPI mode with N1, N0 bits set to return 8-bit data only (N[1:0] = "00"). Upon probing the signals using an oscilloscope, We observed that the CSB pin of the DAC is getting toggled at the same rate as of SCLK when we are trying to read from/write to the DAC.
My first suspect was the SPI core, but it is working properly with other devices. We checked on the board also and found that there is no coupling happening between the CSB and SCLK signals. Is there any setting which I am missing for the device? I had read in the datasheet about the pin-mode of the DAC and put pull-ups on CSB & SDO lines as well as pull-downs on SDIO & SCLK lines.