For my current project I am using BF561 processor and the clock is provided by a Crystal of 100Mhz.
When I connect the emulator to the target using VDSP5.0, I observed the default values of the PLL registers to be as given below
PLL_CTL = 0x1500; whereas the default value should be 0x1400
PLL_DIV = 0x05;
PLL_STAT = 0xA1; whereas the default value should be 0xA2
VR_CTL = 0xDB;
We created a project and tried changing the PLL values for Core Clock = 400Mhz and Sys Clock = 80Mhz using Set_PLL() function given by Analog devices.
But the PLL_STAT is not getting changed.
Can u tell us why PLL is getting bypassed and Core is going in active mode?