AnsweredAssumed Answered

PLL AD9553 locks on wrong frequency

Question asked by GenoMicha on Oct 18, 2012
Latest reply on Oct 24, 2012 by GenoMicha

Hello everybody,

im Using the PLL AD9553 to generate a 6,6MHz Signal out of a 11kHz sqare reference signal. I am using the RefA input and the OUT1 output. The PLL is configured via SPI the A and Y  conrol pins are all connected to GND.

The feedback divider is set to 19800, P1 is set to 60, P0 is set to 10.

When the input Signal is enabled the pll locks and generates the 6,6 Mhz Signal. But sometimes the pll locks to 19,8Mhz and ís working stable on this wrong frequency. After switching off and on the 11kHz reference signal, the pll locks on the correct frequency.

I allready checked all test outputs: PFD feedback = 11kHz, PFD reference = 11kHz. Both signals are stable with 11kHz at 6,6 and 19,8Mhz.

 

Thanks

Micha

Outcomes