I think that I run into the anomaly 480: "Multiple Simulatanous Urgent DMA Requests May Cause DMA System Instability".
I use a DMA descriptor list (with 2 descriptors) for the SPORT0 Tx/Rx DMA configuration. Basically it's a list with descriptors implementing a double buffering "ping/pong" scheme for each the Rx and the Tx channel. The SPORT DMA (3/4) register values should toggle between 2 sets of values. However after some time I get invalid values in some of the registers. The high and low address value words are swapped for example or the config register is filled with the modify value, etc.
I followed the workaround suggestion and set the DMA traffic control values to 1:
DCB_TRAFFIC_PERIOD = 1
DEB_TRAFFIC_PERIOD = 1
DAB_TRAFFIC_PERIOD = 1
MDMA_ROUND_ROBIN_PERIOD = 0
I would like to know if this workaround absolutely excludes this anomaly or is it just a suggestion that might solve the problem? In other words if I set the traffic registers as above, can I still encounter this issue under certain conditions?
My system uses the following DMA channels (possible all at the same time):
DMA1 - MAC RX
DMA2 - MAC TX
DMA3 - SPORT0 RX (continious)
DMA4 - SPORT0 TX (continious)
DMA9 - UART0 TX
DMA11 - UART1 TX (continious)