I have been having some trouble getting the ADV7842 to detect composite signals. I am testing the chip in our design, which uses the 7842 as a front end analog to digital converter that feeds 30-bits of color data and external sync signals (VCLK, HS, VS) into a digital processor. This system has worked using the HDMI input of the 7842.
A pattern generator is used as a video source. Using either a NTSC or PAL video format the read only SDP registers 0x52[3:0] (SDP_STD), 0x5A (SDP_VIDEO_Detected), and 0x59 (SDP_BURST_LOCKED) do not detect a signal. The SDP_STD is always 0 (NTSC) and SDP_VIDEO_DETECT is always low. I physically verified on a termination resistor the video signal looked valid with a 1 Vpp amplitude and double checked XTAL is provided a 28.63 MHz clock. The script "Scripts 1 CVBS" found in the "ADV7842-VER.5.9c.txt" file was used as a base for initializing the device. Our design uses AIN7 so the SDP register 0x83 from 0xB0 to 0x70 to accommodate.
On a side note, I have tried using the internal color bar pattern but our digital processor is measuring the horizontal active width as 270 pixels instead of 720. I believe our digital processor's measurements are accurate because it can measure a 480i, 720p, 1080i, and 1080p correctly when the HDMI input of the 7842 had been used. The external sync frequencies VCLK, HS, and VS are accurate so I am wondering if I missed setting a "recommend" register that corrects a blanking period.