I'm working with the TS201 tigersharc using a toppology where 3 processors (P0, P1 & P2) are
connected to shared cluster bus. In this topology P0 is the master processor.
My aim is that P0 will be able to reset the whole DSP group (that is to reset P1 and P2 and after that
to reset itself) when desired. After such reset the 3 DSPs are supposed to re-boot from flash and run
again from start.
The code I wrote for this resides in P0 and simply sets the SWRST bit in the EMUCTL of P1 & P2 and later on
sets the SWRST in P0 (that is P0 sets its SWRST bit within its own EMUCTL).
What I see is that P1 & P2 reboot as expected but P0 does not seem to receive sofware reset at all.
Before I issue the SWRST in P0 I changed the NMOD in SQCTL to supervisor mode but this also did not yield the expected s/w reset.
Is there any problem for a tigersharc to reset itself using the SWRST bit in its own EMUCTL?
If not, what should I do in order to make P0 reset itself this way?
I'll appreciate any insights?