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AD829 stability

Question asked by mbart on Oct 17, 2012
Latest reply on Nov 16, 2012 by mbart

Hello,

 

Is the AD829 stable in the following conditions ? What is the Phase Margin ?

- CL=150pF capacitor load

- RL=~1kohms resistor load

- Vs = +/- 5V

- Ccomp = 15pF to inverted input

 

I attached the schematic (VEE = -5V and VCC = +5V).

 

Can I simulate the phase margin with PSPICE and how ? Is the model realistic in theses conditions ?

 

Thanks for your answer,

 

Mathieu

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