Hello,

I'm want to use the AD5933 eval. board for electrochemical impedance measurement in a broad range of frequencies (1Hz- 100kHz).

I read in UG-364 and EVAL-CN0217-EB1Z docs that I have to scale the system clock to analyze frequencies below 1kHz.

The table "Experimental Lower Frequency Limits vs. MCLK" (table 2 in UG364) shows the experimental lower frequency limit in function of the system clock but I want also to calculate the upper frequency limit but I'm not sure how to do it.

In documentation (UG-364 and EVAL-CN0217-EB1Z) people of AD say that DDS reference clock is MCLK / 4, and the max DDS frecuency output is DDS reference clock / 8. I understand that Fout,max = Fdds * M / 2^27 = Fdds * 2^24 / 2^27 = Fdds / 8. So, for a 4MHZ system clock Fout,max = 125kHz but the maximum frequency range of transmit stage is 100kHz (from AD5933 datasheet).

Moreover, the example in doc says that for a 4MHz system clock the DDS reference clock is 1MHz and the maximum output frequency is 1/32*1MHz = 31.25kHz. So, there is a factor of 4 (125 / 4 = 31.5) that I don't know where it comes from. It seems that system clock is divided by 4 twice ( MCLK/(4*8*4) ), why?. Does anybody know if it it's the rigth way to calculate the upper frequency limit? And where does this factor of 4 come from?

Thanks in advance,

Ignasi

Hi Ignasi,

The AD5933 was originally designed for a max frequecny of 100kHz so, it was not characterized for higher frequencies.

Moreover, the analog block includes a RC filter of 150kHz...

So, you can get higher output frequencies but this is not guaranteed.

Answering your second question, table 2 are experimental values.

Ah!! there is a typo error, the ADC clock frequency is divided by 4 as well, and needs 4 clocks to gather a new sample.

Let me know if something is not clear, please.

Regards,

Miguel