I have made a design in which ADCLK846 is used as the synchronizing clock destribution IC between two AD9739s . It seems that the output to output skew of ADCLK846 (Max 65ps) is two large to synchronizing AD9739s . Because the sync controller of the slave AD9739 can't lock while the master AD9739 works well . Among the readback values of register 0x2A , 0x21 , 0x0D of two AD9739s , only 0x0D [5:4] ( =00 ) of slave AD9739 indicate that slave AD9739 works incorrectly . The other readback values is OK , just as same as the datasheet provided.
Does the ADCLK846 is the reason ? But the DACCLK of two AD9739s is just 1.1 GHz ,SYNCO 275MHz . Is the 65ps skew of SYNCIN clock really too large to meet the timing margin of this two AD9739 ?
If the ADCLK846 is the reason , how can I make a remedy without remake a PCB ?