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SRAM vs. SDRAM --- Need lowest power for battery powered product

Question asked by ljanis on Oct 8, 2012
Latest reply on Dec 12, 2012 by TomA

The Engineerzone(r) has a great post http://ez.analog.com/message/1441#1441 “SRAM vs. SDRAM” and I would like to hear more pointed to my battery powered application.  We are using two Blackfins (512 and 522) and need to add external memory. We are pushing the speed of both processors and so cannot ignore performance, but power is still primary. The goal is to keep the amount of additional power to less than 100 mW total (core and I/O) for each processor. Each processor will be running continuously and executing code from both internal and external memory.  My concern is that SRAM takes an address cycle for every read or write while the SDRAM may be able to do sequential reads or writes and overall take less bus power and cycles depending on what the memory controllers can do on the Blackfins.  The addition of a cache and any pipelining makes this more complex since I cannot predict the code sequences.   We have asked several engineers to help and have received great inputs, but no one yet has provided a quantitive answer.  Lastly, smaller memory (4Mbit or 8Mbit) would be enough to meet our needs.   Any response would be appreciated.

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