The tables for the ADC data rate are based on a 125KHz Fadc which is 16MHz / 128. However the clocking architecture block diagram suggests the ADC clock can come from either UCLK or PCLK. Bearing in mind that both of these clock paths can be subject to division is it the case that the ADC cannot be used unless it is fed from a 16MHz clock or could you use a slower clock and just adjust the filter calculations accordingly?
Secondly, some time in June this year, a spreadsheet was posted here to calculate data rates and filter responses (aducm360_freq_response_update.xls). Using that spreadsheet and trying various combinations of SF and AF to get a 50Hz data rate (actually 50.08Hz is the closest) the only combination that gives a filter notch at 50Hz is SF = 125, AF = 0. Unfortunately this setting gives a settling time of 3/Fadc instead of 1/Fadc and in my tests gives much more noise than a setting in which AF is non-zero. Can you confirm that the 50Hz notch is indeed only present when AF = 0 and that any combination of SF and AF that gives a 50Hz data rate but with AF > 0 will not filter 50Hz interference?