I'm experiencing a problem with dividers for TWI interface.
The dividers in TWI_CLKDIV seem to be higher than should be by 3.
With SCLK = 100 MHz, and PRESCALE = 10 the reference frequency for TWI is 10 MHz as it should be.
With TWI_CLKDIV = CLKHI(50) | CLKLOW(50) I got TWI frequency of 94.3 kHz. To get 100 kHz I have to program TWI_CLKDIV = CLKHI(47) | CLKLOW(47).
With different duty cycle and different frequencies I got always offset by 3 for each divider. I didn't find this issue in anomaly list.
Could anyone confirm this behavior?