We have a new design with an adv7842 and an external DDR ram, MT46V16M16P-6T from Micron Technology, Inc.
Setting up the adv7842 to receive CVBS on Ain10.
When I enable the Frame time-based correction (TBC ) the signal out from the adv7842 becomes extremely noisy.
I have followed the recommended settings from the documentation (in particular 12.5.1 from UG-214).
The same settings works fine on the EVAL-board.
By cooling down the adv7842 and the Ram during configuration (reset of memory controller sdp_io 0x60) it sometimes
shows an improved performance. This last until warmed up again.
From this we assume that the problem is timing-related.
Could you provide more information about the configuration of the memory controller ?
Registers such as:
sdp_io 0x74, 0x75, 0x79, 0x7a, 0x7b and so on.
Note also the confusion/error in the description of the "tristate memory interface" configuration.
UG-214 3.3.7. As far as I can work out is the memory interface in tristate when sdp_io 0x2984] is "1"