We are facing problem while transmitting data byte by byte using TX interrupt of SPORT ADSP21992.
We have used External clock for SPORT of frequency 5KHz, coming from other processor.
The configuration of SPORT transmit Registers is as follow:
1) SP_TCR = 0x A6E1
i.e We have configured word length = 8bits, Internal TFS - active high .late framing and data dependent TFS.
As soon as we enable TSPEN bit in SP_TCR , we get TX interrupt which is desired. We fill data in SP_TX Register in TX ISR and wait for next interrupt to fill next data.
The problem here is that the interrupt is triggered only for the first time and hence interrpt based transmit does not work. We observed that if we add delay around 2.5mSec, interrupt comes for every byte transfer and transmit works fine.
We studied 2199x anomaly where same problem is mentioned in Anomaly6- 6. SPORT generates TFS (Transmit Frame Sync) one clock cycle earlier than expected when configured for data-dependent and early frame sync mode.
(Refer to attached 2199x anomaly document.)
But as per the document this problem is not applicable if
A] The frame sync is configured to be data independent.
B] The frame sync is configured to be late frame sync.
C] DMA mode of data transfer is used.
The condition B is satisfied in our case, but still we are facing the same problem. Our code works ok with workaround (2b) mentioned in the document.
Please help us to find out the correct reason for this problem.
Thanks in advance for your time.
P.S. We see the same problem when we configure the DMA too. We are yet to try the said workaround with DMA option.