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AD-FMCOMMS1-EBZ  clocking

Question asked by Stepper Employee on Sep 28, 2012
Latest reply on Jan 10, 2013 by AdrianHolmes
  1. Can AD-FMCOMMS1-EBZ be driven by a clock provided  by the FPGA through a pin (or complementary pair of pins) of the FMC interface?
  2. If so, can the upconverter/DAC and the ADC/downconverter be driven from separate clocks from the FPGA?
  3. Does the COMMS1 have only a single master onboard clock, or can it strobe its DAC and ADC separately?


We want to use a single ML605 with Simulink’s GigE-based FIL (FPGA-in=the-loop) environment to demonstrate independently-clocked transmitter (upconvter/DAC) and receiver (ADC/downconverter).  We do this now with a pair of FMC150 boards:  one in the low pin count FMC slot, the other in the HPC FMC.  Bringing up two FMC150s on a single host, a seemingly easy task, has proven to be unexpectedly challenging and time-consuming.


Has anyone successful brought up two AD-FMCOMMS1-EBZ , independently clocked either from within or from different clock regions within the FPGA, on a single ML605?


Is there any reason this might be difficult to do?