Can the operation of the DAC update rate setting (DACxCON, DACCLK) for the ADuC702x devices be clarified?
If the DACxDAT register is written to I presume either the DAC ladder switches and/or DAC output are not updated immediately. DACCLK configures the update to take place either on the next HCLK edge, or a Timer 1 underflow/overflow (?) after the write to DACxDAT? In the case of Timer 1, does its interrupt have to be enabled? The description in the data sheet for Timer 1 does not mention any relationship with the DAC or show anything in the Timer 1 block diagram.