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On using clock doubler option of AD9963 for low jitter performance?

Question asked by Wavefunction on Sep 26, 2012
Latest reply on Sep 26, 2012 by larrywelchusa



In our project, we have a low-jitter oscillator source of 30 MHz directly clocking the AD9963, without using the on-chip DLL section. Since, we want to sample the ADCs and DACs with higher rate, we intend to use the Clock-Doubler option in AD9963 [Page 47: Configuring the Clock Doublers]. (As noted in the datasheet, I'm also aware that interpolation and decimation should not be used in this case).


However, I'm wondering if the usage of clock-doubler option would degrade the noise and SFDR of the data converters in a significant way! My concern arises from the DLL section of the datasheet. [Page 45: Using DLLCLK as the data converter sampling clock signal may degrade the noise and SFDR performance of the converters].

Can I assume that this DLLCLK section is different from the Clock-Doubler section and that this warning only applies if we use the DLL clock?


Hope, I have made myself clear!

Kind Regards!