I use three DDS chips in my design, one master (AD9911) and two slaves (AD9959). The REF_CLKs of these three DDS are from the same source (24.8832MHz) . The SYNC_OUT of AD9911 is connected to the SYNC_IN of two AD9959. PLL divider ratio register bits of these three DDS are set to 20, so they are all running at the internal clock of 497.664MHz. And I set bit[7:0] of FR2 register to 0x40 in AD9911, and 0x83 in two AD9959 to use the synchronization function between the master and slaves.
During the test, I want to check whether the slave can report an out of sync status. So I write 0x00 to b[7:0] of FR2 of the master to disable the SYNC_OUT. In this way, I expect to create deliberately an out of sync situation in the two slaves. But when I read FR2 of the two slaves, b5 is never set.
Why is that? How do I create an out of sync case where I can actually see that status bit gets set high?
Thank you very much!