1. Can LVDS clock (with 400mV common mode) be used as CLKPand CLKN
2. For 200MSPS input (I = 200; Q = 200), should the clock rate be 200 or 400Hz? According to the Datasheet, the sampling clock (DSS)
can sample at both positive and negative edge. So the input clock should be 200 MSPS only , right?
3. Does the DCO pin deliver DSS clock to the Data source? If the DCO is same as DSS, is it sufficient that we
place the data with respect to DCO clock (with appropriate settling and hold time) and avoid all initial calibration involving SMP, SEEK and HLD bis.
We are planning to use separate clock source for both DAC and FPGA. So the start up time for DAC clock will vary every time during power-on.
In this case, we cannot afford to do calibration exercise each and every time after power-up. So can we just use DCO
for guideline to place the data or should we use common clock source to FPGA and DAC.
4. The DAC output compliance voltage is 1V. Can we increase this value by ising I-V converter based on Op-amp?
5. We are not clear of LVDS input specifications. What is the Maximum differential swing and what is the common mode voltage? Can
we use AC-coupling? Do you have any suggestions/documents on LVDS interface to DAC.