Datasheet on page 11 define Absolute Maximum Ratings:
- Power line 1.8V AVDD, PVDD and VDD must be in +-0.3V from each other.
- VDD_SDRAM (3.3V or 2.5V) must be above AVDD, PVDD and VDD on -0.3…2V.
- TVDD (3.3V) must be above CVDD (1.8V) on -0.3…2.2V.
- DVDDIO (3.3V) must be above VDD_SDRAM (3.3V or 2.5V) on -0.3…3.3V
- “Stresses above those … may cause permanent damage to the device” and “Exposure to absolute maximum rating conditions for extended periods may affect device reliability”.
On next page Datasheet define Power-up sequence:
- 3.3V (DVDDIO, TVDD) up to 3.3V
- Next 2.5V (VDD_SDRAM) from 0 to 2.5V. But in this term Rule-3 is violated: TVDD-CVDD=3.3V (must be -0.3…2.2V). Duration ~100…150uS. “ADV7842_Eval_Note_RevA_14_December_2010.pdf” ( ) has additional delay 50mS.
- Next 1.8V (AVDD, PVDD, VDD and CVDD) from 0 to 1.8V. But in this term Rule-2 is violated: VDD_SDRAM- AVDD=2.5V (must be -0.3…2V). Duration ~50…100uS. “ADV7842_Eval_Note_RevA_14_December_2010.pdf” has additional delay 50mS.
“EVAL-ADV7842-7511_Rev1p0.pdf” (http://ez.analog.com/docs/DOC-1681) made powering VDD and AVDD, PVDD from different chips: VDD have Ramp-Up 7mS (http://www.analog.com/static/imported-files/data_sheets/ADP1715_1716.pdf) - Rule-1 is violated: AVDD,PVDD – VDD = 1.8V (must be +-0.3V), duration 7mS.
Are these violations insignificant or this design Power-up sequence is no good?