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SRC on 21469 with heavy jitter

Question asked by Hfuhrhurr on Sep 21, 2012
Latest reply on Sep 27, 2012 by Harshit.Gaharwar

Hi,

 

I have a problem with the implementation of an SPDIF receiver and the SRC.

My system looks like this (ugly but quick drawing)

ADSP21469_SRC_Problem.png

Currently I am using a measurement system to input a 1kHz sine tone with 96kHz into the DIR and measure the response via the DIT. This works fine, I have a very stable sine with high THD value and no visible problems.

Additionally, I am sampling from the DAC which gets the same signal passed through the SRC as seen above. The DAC runs on 96kHz and the SRC gets the clocks at the output from the PCG.

When I look at the measured sine in the time domain, I can see that the analog sine moves against the digital sine signal about 3-4 samples, that is about 40 microseconds. Since the pure digital connection seems to be fine, I don't have any explanation for this.

Maybe someone can help me out with this.

 

This is my init code for the peripherals

void InitPCG(void)
{
    // CLKIN is used as input source (12.288 MHz)
    // PCG A outputs MCLK (12.288MHz) and no frame sync
    // PCG B outputs SCLK (6.144MHz) and frame sync 96kHz
    // Dividers are 2 for SCLK and 128 for frame sync

    //FS Divisor = 4 & FS Phase 20-29 =0, Enable Clock
    *pPCG_CTLA0 = ENCLKA | (0<<20);  

    //CLK Divisor = 0x1 & FS Phase 0-9 =0, Use CLKIN as source
    *pPCG_CTLA1 = 0x1;  

    //FS Divisor = 128 & FS Phase 20-29 =0, Enable Clock
    *pPCG_CTLB0 = ENCLKB | ENFSB | (0<<20) | 0x80;  

    //CLK Divisor = 2 & FS Phase 0-9 =1, Use CLKIN as source
    // If the phase shift is one, the frame sync output transitions 
    // one input clock period ahead of the clock transition
    *pPCG_CTLB1 = 0x2 | (1 << 20);  


}

void InitSRC(void)
{
    * pSRCCTL0 = SRC0_IN_I2S | SRC0_OUT_I2S | SRC0_OUT_24;
    * pSRCCTL0 |= SRC0_ENABLE;

}

void InitSPDIFRx(void)
{
    *pDIRCTL=0x0;

}

void InitSPDIFTx(void)
{
   *pDITCTL = (DIT_EN|DIT_IN_I2S|DIT_FREQ256|DIT_AUTO);
}

 

and this is my SRU init

 

// This function will setup the SRU Registers
void InitSRU(void)
{

    //
    // Connect Clocks
    //    
    //Generating Code for connecting : PCG_CLKA to DAI_PIN13 (OMCK)
    SRU (HIGH, PBEN13_I); 
    SRU (PCG_CLKA_O, DAI_PB13_I); 

    //Generating Code for connecting : PCG_CLKB to DAI_PIN4 (CX_SCLK)
    SRU (HIGH, PBEN04_I); 
    SRU (PCG_CLKB_O, DAI_PB04_I); 

    //Generating Code for connecting : PCG_FSB to DAI_PIN5 (CX_LRCLK)
    SRU (HIGH, PBEN05_I); 
    SRU (PCG_FSB_O, DAI_PB05_I); 

    //Generating Code for connecting : PCG_CLKB to SRC0_CLK_OP
    SRU (PCG_CLKB_O, SRC0_CLK_OP_I); 

    //Generating Code for connecting : PCG_FSB to SRC0_FS_OP
    SRU (PCG_FSB_O, SRC0_FS_OP_I); 


    //
    // Connect Data
    //    

    //Generating Code for connecting : SRC0_DAT_OP to DAI_PIN1 (CX_SDIN1)
    SRU (HIGH, PBEN01_I); 
    SRU (SRC0_DAT_OP_O, DAI_PB01_I); 

    // 
    // SPDIF and SRC
    //    
    //Generating Code for connecting : DAI_PIN20 (SPDIF_IN) to DIR
    SRU (LOW, PBEN20_I); 
    SRU (DAI_PB20_O, DIR_I); 

    //Generating Code for connecting : DIR_CLK to SRC0_CLK_IP
    SRU (DIR_CLK_O, SRC0_CLK_IP_I); 

    //Generating Code for connecting : DIR_FS to SRC0_FS_IP
    SRU (DIR_FS_O, SRC0_FS_IP_I); 

    //Generating Code for connecting : DIR_DAT to SRC0_DAT_IP
    SRU (DIR_DAT_O, SRC0_DAT_IP_I); 

    //Generating Code for connecting : DIR_DAT to DIT_DAT
    SRU (DIR_DAT_O, DIT_DAT_I); 

    //Generating Code for connecting : DIR_CLK to DIT_CLK
    SRU (DIR_CLK_O, DIT_CLK_I); 

    //Generating Code for connecting : DIR_FS to DIT_FS
    SRU (DIR_FS_O, DIT_FS_I); 

    //Generating Code for connecting : DIR_TDMCLK to DIT_HFCLK
    SRU (DIR_TDMCLK_O, DIT_HFCLK_I); 

    //Generating Code for connecting : DIT to DAI_PIN19 (SPDIF_OUT)
    SRU (HIGH, PBEN19_I); 
    SRU (DIT_O, DAI_PB19_I); 


 

Best regards,

 

Rainer

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