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About the signal FRSTDATA on AD7606

Question asked by zchong on Sep 19, 2012
Latest reply on Sep 26, 2012 by KarenNE



I have a question about the signal FRSTDATA on AD7606, this signal is used for indicating when the V1 is read. Now i connect this pin to a CPU's GPIO, normally the chip seletion signal CS and control signal RD come almost at the same time, as soon as i read the V1 data,i read the GPIO state to jude the data is V1 channel or not,but the RSTDATA signal will be changed to three-state  due to CS is high  at this time, so it's not reliable to jude the V1 channel by this method. Any suggestion?


If  AD7606's CS is always pulled down, use CPU's CS and RD as the AD7606's RD may be OK, but i don't kown this will affect databus or not?





Best Regard,