I need to interface an external memory to the ADUC812 via a FPGA. The data read time in the memory is very large (222 ns). The ADUC timing PSEN low to valid instruction is only 145ns and the memory will not be able to give instruction within this time. But i have managed to initiate the program memory read with the ALE since ALE low to valid instruction is 234ns and it works. But the issue is with the ALE low to PSEN low timing which is 53ns minimum. Assuming PSEN becoming low in 53ns after ALE low and valid instruction is received at 222ns after ALE low my design will not satisfy the PSEN low to valid Instruction timing. Will this cause issue? Since the ADUC will be driving the ALE and PSEN on MCLK will it be OK to satisfy any 1 timing for the valid instruction (either from PSEN low or ALE low)?